Integrated circuits (ICs) frequently have buried layer conductive elements, such as n-type buried layers under circuits to reduce latchup. Such buried conductive elements are typically several microns below the surface of the IC substrate. Surface elements, such as deep wells, extend from the substrate surface and connect to the buried conductive elements. It is important that photolithographic patterns to define surface elements be aligned with the buried elements. Alignment of patterns with buried layers is difficult, due to a lack of clear features from the buried layers that are visible at the surface of the substrate. As lateral dimensions of structures in ICs shrink, as articulated by Moore's Law, the difficulty of alignment increases. Verification of alignment is a costly, time consuming and destructive process involving cross-sectioning a pilot wafer and measuring the alignment with a Scanning Electron Microscope (SEM).